This article proposed a simple self CASCODE RGC AMPLIFIER configuration to increase the gain and bandwidth. The CASCODE AMPLIFIER eliminates the miller capacitance between input and output and facilitates high gain, high input and output impedance with high bandwidth. However, the CASCODE AMPLIFIER requires relatively high supply voltage for proper operation and it decreases the output voltage swing by overdrive voltage. These issues are overcome by self CASCODE based RGC AMPLIFIER; even though it has low bandwidth due to the presence of one of its pole at low frequency. The bandwidth and output impedance of the conventional RGC has increased using a split length compensation technique. To improve the overall performance of the AMPLIFIER, introduced a simple self CASCODE RGC without using additional passive elements. The expression of gain and output impedance for the proposed AMPLIFIER is derived using small signal analysis. The calculated value of voltage gain for the projected circuit is 58. 37 dB which is more than the self CASCODE based RGC. The power dissipation of the proposed circuit is 1. 07 μ Watt and it was compared with CS, CASCODE, self CASCODE and SC based CASCODE, RGC, SC based RGC AMPLIFIERs.

Background and Objectives: In this paper, a novel structure as a Folded-Mirror (FM) Trans-impedance AMPLIFIER (TIA) is designed and introduced for the first time based on the combination of the current-mirror and the folded-cascade topologies. The trans-impedance AMPLIFIER stage is the most critical building block in a receiver system. This novel proposed topology is based on the combination of the current mirror topology and the folded-cascade topology, which is designed using ACTIVE elements. The idea is to use a current mirror topology at the input node. In the proposed circuit, unlike many other reported designs, the signal current (and not the voltage) is being amplified till it reaches the output node. The proposed TIA benefits from a low input resistance, due to the use of a diode-connected transistor, as part of the current mirror topology, which helps to isolate the dominant input capacitance. So, as a result, the data rate of 5Gbps is obtained by consuming considerably low power. Also, the designed circuit employs only six ACTIVE elements, which yields a small occupied chip area, while providing 40.6dBΩ of trans-impedance gain, 3.55GHz frequency bandwidth, and 664nArms input-referred noise by consuming only 315µW power using a 1V supply. Results justify the proper performance of the proposed circuit structure as a low-power TIA stage.Methods: The proposed topology is based on the combination of the current mirror topology and the folded-cascade topology. The circuit performance of the proposed folded-mirror TIA is simulated using 90nm CMOS technology parameters in the Hspice software. Furthermore, the Monte-Carlo analysis over the size of widths and lengths of the transistors is performed for 200runs, to analyze the fabrication process.Results: The proposed FM TIA circuit provides 40.6dBΩ trans-impedance gain and 3.55GHz frequency bandwidth, while, consuming only 315µW power using a 1V supply. Besides, as analyzing the quality of the output signal in the receiver circuits for communication applications is vital, the eye-diagram of the proposed FM TIA for a 50µA input signal is opened about 5mV, while, for a 100µA input signal the eye is opened vertically about 10mV. So, the vertical and horizontal opening of the eye is clearly shown. Furthermore, Monte-Carlo analysis over the trans-impedance gain represents a normal distribution with the mean value of 40.6dBΩ and standard deviation of 0.4dBΩ. Also, the value of the input resistance of the FM TIA is equal to 84.4Ω at low frequencies and reaches the value of 75Ω at -3dB frequency. The analysis of the effect of the feedback network on the value of the input resistance demonstrates the input resistance in the absence of the feedback network reaches up to 1.4MΩ, which yields the importance of the existence of the feedback network to obtain a broadband system.Conclusion: In this paper, a trans-impedance AMPLIFIER based on a combination of the current-mirror topology and the folded-cascade topology is presented, which amplifies the current signal and converts it to the voltage at the output node. Due to the existence of a diode-connected transistor at the input node, the input resistance of the TIA is comparatively small. Furthermore, four out of six transistors are PMOS transistors, which represent less thermal noise in comparison with NMOS transistors. Also, the proposed Folded-Mirror topology occupies a relatively small area on-chip, due to the fact that no passive element is used in the feedforward network. Results using 90nm CMOS technology parameters show 40.6dBΩ trans-impedance gain, 3.55GHz frequency bandwidth, 664nArms input-referred noise, and only 315µW power dissipation using a 1volt supply, which indicates the proper performance of the proposed circuit as a low-power building block.

In this work, a low power, low voltage and high gain operational AMPLIFIER is proposed. For this purpose, a negative resistance structure is used in parallel with output to improve the achievable gain. Because of using self CASCODE transistors in the output, the proposed structure remains approximately constant in a relatively large output voltage swing causing an invariable gain. To evaluate the proposed method an op amp was designed in 0.18mm CMOS technology. The simulation results showed a gain of 84dB, unity gain bandwidth of 12.45MHz and phase margin of 81 degree, with 1V power supply and 1pF load capacitor.

In this paper, an ultra-broad bandwidth, low noise, and high gain-flatness CMOS distributed AMPLIFIER (CMOS-DA) based on a novel gain-cell is presented. The new gain-cell that enhances the output impedance as a result the gain substantially over conventional RGC is the improved version of Regulated CASCODE Configuration (RGC). The new gain-cell based CMOS-DA is analyzed and simulated in the standard 0.13 mm-CMOS technology. The simulated results of the proposed CMOS-DA are included 14.2 dB average power gain with less than±0.5 dB fluctuations over the 3-dB bandwidth of 23 GHz while the simulated input and output return losses (S11 and S22) are less than -10 dB. The IIP3 and input referred 1-dB compression point are simulated at 15 GHz and achieved+8 dBm and -6.34 dBm, respectively. The average noise figure (NF) in the entire interest band has a low value of 3.65 dB, and the DC power dissipation is only 45.63 mW. The CMOS-DA is powered by 0.9 V supply voltage. Additionally, the effect of parameters variation on performance specifications of the proposed design is simulated by Monte Carlo simulations to ensure that the desired accuracy is yielded.

A multiphase sinusoidal oscillator (MSO) using dual output voltage differencing buffered AMPLIFIER (DO-VDBA) is presented in this paper which provides n equally spaced phase sinusoids of equal magnitudes. The proposed MSO topology is realized using the first order all pass network (APN). In the proposed structure the output voltages are made available at low impedance nodes which makes the proposed MSO easy for cascadability. Making the proposed structure a resistorless structure is a major challenge. The main benefits of the structure are easy integration and less power losses. The formulation of frequency and condition of oscillation is derived mathematically. The oscillation frequency can be tuned electronically, is an added advantage of the proposed MSO. The effect of device non-idealities is also discussed in the study. To assess the proposed MSO performance further Monte Carlo analysis was carried out. The workability of the proposed structure is verified through SPICE simulations for a three (n=3) and four (n=4) phases MSO, and the obtained simulated results are in close agreement with the theoretical values. The total harmonic distortion (THD) is found to be quite low.

An optical communication receiver system is presented in this research using 65nm CMOS, which consists of three lowpower ACTIVE differential stages as Limiting AMPLIFIER (LA) following an ultra-low-power RGC-Based Transimpedance AMPLIFIER (RB-TIA). The presented ACTIVE circuit of the RB-TIA is followed by a gain stage that extends the-3dB frequency of the circuit by creating a resonance for the load capacitance. Thus, needless of consuming extra power, a wide-bandwidth circuit has been designed. In addition, employing ACTIVE-inductor loads within the LA stages enables obtaining a 5Gbps receiver system. The RB-TIA consumes 573μ W and provides 3. 52GHz frequency, while the complete optical receiver consumes only 4. 76mW power to provide-3dB frequency of 3. 5GHz and high gain of 80dB (10’ 000). The circuits have been mathematically presented and discussed, and simulations have justified the presented circuit design.

In this study an ultra-broad band, low-power, and high-gain CMOS Distributed AMPLIFIER (CMOS-DA) utilizing a new gain-cell based on the inductively peaking cascaded structure is presented. It is created by cascading of inductively coupled common-source (CS) stage and Regulated CASCODE Configuration (RGC). The proposed three-stage DA is simulated in 0.13 mm CMOS process. It achieves flat and high S21 of 26.5 ± 0.4 dB over the frequencies range from DC up to 13 GHz 3-dB bandwidth, and it dissipates only 9.95 mW. The IIP3 is simulated and achieved -10 dBm at 6 GHz. Also, simulated input referred 1-dB compression point at 6 GHz achieves the value of -20 dBm. Both input and output matches are better than -11 dB. To obtain the low power and high gain requirements, the advantages of the bulk terminal are exploited in the proposed CMOS-DA. It adopts the method of forward body biasing in output MOS transistor to achieve higher transconductance and lower power consumption. Additionally, the Monte Carlo (MC) simulation is performed to take into account the risks associated with various input parameters which they receive little or no consideration in simulating of designs utilizing ideal components. MC simulation predicts an estimate of the good accuracy performance of the proposed design under various conditions.